By Richard J. Peterson
This ebook makes a speciality of suggestions for minimizing strength dissipation in the course of attempt program at common sense and register-transfer degrees of abstraction of the very huge scale built-in (VLSI) layout movement. After a survey of current recommendations for strength restricted checking out of VLSI circuits, numerous try out automation ideas are provided for lowering energy in scan-based sequential circuits and BIST facts paths. Nicolici is affiliated with McMaster collage, Canada. Al-Hashimi is affiliated with the collage of Southampton, united kingdom.
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Extra info for Power-Constrained Testing Of Vlsi Circuits
5 Internal Test vs. 7. 3) is significantly modified when reordering scan cells and and test vectors and Approaches to Handle Test Power 39 The new sequence obtained after reordering will lead to lower switching activity and hence lower power dissipation due to higher correlation between consecutive patterns at the primary and pseudo inputs of the CUT. Further benefit of the post-ATPG technique proposed in  is that minimization of power dissipation during test application is achieved without any decrease in fault coverage and/or increase in test application time.
In order to consider power during test scheduling‚ the power dissipated by the block under test needs to be modeled using generic power models. The power profiles capture the power dissipation of a block over time when applying a sequence of test vectors to the primary and pseudo inputs of the block. The power profiles give cycle-accurate descriptions of power dissipa- 24 POWER-CONSTRAINED TESTING OF VLSI CIRCUITS tion which makes them too complex to be considered in the test scheduling process.
The approaches in [127, 140] adapt the scan chain for low power using equal multiple scan chain divisions. A two dimensional scan array solution was proposed in , while an interleaving architecture that adds delay buffers between the scan chains to reduce the peak power of the capture cycle was introduced in . 4 37 Test-per-Clock vs. Test-per-Scan In a scan environment, a test pattern is applied after shifting in the test vector and shifting out the test response. Therefore, the testing scheme for a scan methodology is called test-per-scan, which is unlike the test-per-clock testing scheme where a test pattern is applied in every clock cycle.
Power-Constrained Testing Of Vlsi Circuits by Richard J. Peterson